1. Field of the Invention
This invention relates to sequential logic circuits implemented in a particular bipolar logic family and, more particularly, relates to sequential logic functions such as flip-flops or latches which are implemented with inverter function logic gates.
2. Discussion of Background and Prior Art
Digital computers utilize both combinational and sequential logic circuits in their processing units. Combinational logic circuits perform a preset logical operation upon variable inputs and produce an immediate output of the results. The combinational logic functions are implemented with particular ones of the available integrated circuit logic gates of the types which are available with one of the popular logic families such as transistor-transistor logic, emitter-coupled logic, resistor-transistor logic or are implemented with particularized logic gates such as those disclosed in Z. E. Skokan, "Logic Gate", U.S. Pat. No. 3,643,109. See generally D. A. Hodges et al., Analysis and Design of Digital Integrated Circuits, Chapter 7, "Bipolar Digital Gate Circuits", (McGraw-Hill 1983); and H. W. Gschwind et al., Design of Digital Computers, pp. 64-100. Combinational logic circuits which are implemented in inverter function logic are disclosed in the copending U.S. application Ser. No. 06/588,919 of Price et al., "Combinational Logic Circuits Implemented With Inverter Function Logic", filed on even date herewith.
Sequential logic circuits perform the function of storing previous input information. They retain a state which is set up by the most recently received data. As basic flip-flops or as latches they, too, are fabricated from available integrated circuit logic gates or are implemented with particularized logic gates, as described above. In a typical digital computer, integrated circuit logic gates based on various logic families may be utilized, especially if they are available off the shelf. Where customized circuits are fabricated, due to process limitations or to the desire to simplify the interconnection schemes, it is at times desirable to utilize a single logic family when implementing both combinational and sequential logic circuits. Such a universal logic gate having unique properties and based upon a variation of ECL logic is disclosed in the co-pending U.S. application Ser. No. 06/588,476 of J. E. Price and L. W. DeClue, "Inverter Function Logic Gate", filed on even date herewith and now as U.S. Pat. No. 4,605,871. Briefly, an individual inverter function logic gate is capable of performing logical operations on the complement of one or more of the input variables without having to use a discrete inverter to produce the complementary value. Such individual inverter function logic gates may be combined to fabricate sequential logic circuits which have preferential properties over prior art sequential logic circuits.
Sequential logic circuits include flip-flops, latches and registers. The logical operation of sequential logic circuits is well known. See, e.g., H. W. Gschwind et al, Design of Digital Computers, Chapter 5, "Storage Elements", pp. 122-154. Sequential logic circuits may be implemented generally by means based upon various types of physical effects. Thus, mechanical, electrical, magnetic, optical, acoustic, or cyrogenic means may be used; molecular and atomic effects may also be used. Electrical implementation and particularly implementation with integrated circuits fabricated with bipolar logic of inverter function logic, as described below, is contemplated in the present invention.
When sequential logic circuits are implemented in an integrated circuit format they are based on one or more of the basic bipolar logic families. For high performance digital computers and other applications where high speed products are desired, the logic family of choice would likely be emitter-coupled logic. Latches implemented in emitter-coupled logic are shown, for example, in the prior art FIGS. of 3, 7, 11 and 15. In these figures of prior art devices the C input line designates the clock input and the D input line designates the data input. It is the previous state of D that is stored so that no other inputs are required, except for R which signifies reset, as shown in FIG. 12. For conventional ECL-based latches the complement of the clock has to be generated in order to permit the latch operation to be performed; this typically requires the use of a separate OR/NOR gate such as gate 70 in FIG. 7 or gate 105 in FIG. 11. Also, the number of individual gates required for ECL-based sequential logic circuits may be undesirably high.